The dilemma between improving performance and reducing a size of semiconductor memories has long been a focus of researchers. With respect to this dilemma, the two major types of semiconductor memories, static random access memory (SRAM) and dynamic random access memory (DRAM), both have advantages and disadvantages. An SRAM can retain its data content as long as a power supply to the SRAM is maintained. However, an SRAM, typically including six field effect transistors (FET), is large in size. On the other hand, a DRAM is usually much smaller than a SRAM in size. A DRAM is disadvantageous in that the stored charge (data) on a capacitor of the DRAM is dynamic, which needs to be refreshed periodically. In addition, a DRAM is also slower than a SRAM because the single rail sensing signal of the DRAM is generated through the charge sharing between the cell node and the bit line (BL) through a thick gate access device. In contrast, the SRAM sensing signal is generated by the active thin gate n-channel filed effect transistors (NFET) pulling down one of the bit line (BL) pair.
Efforts have been made to reduce the size of a SRAM. For example, there are some proposals of integrating a lateral PNPN thyristor (also referred to as a silicon controlled rectifier or SCR) into the complementary metal-oxide semiconductor (CMOS) technology to reduce cell size. However, the proposed memory with a lateral PNPN and a pass gate is not static. In addition, a lateral PNPN is difficult to fabricate and relatively large due the planar devices which cannot be implemented underneath the silicon surface. Other approaches include four transistor (4T) SRAM which does not successfully reduce the overall size of the memory cell.
In view of the foregoing, it is desirable to further reduce the size of SRAM memory cells. The present state of the art technology does not provide a satisfactory solution to this problem.